Integrated circuit (IC) technologies are constantly being improved. Such improvements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Similarly, semiconductor packages are becoming smaller and including more advanced devices, exemplified by the use of chip-scale packages (CSPs).
A conventional use for semiconductor packages is to mount a package on a printed circuit board using a Ball Grid Array (BGA) technique. In this approach, the semiconductor package is mounted to the printed circuit board using solder balls that bond to metal contact pads on the printed circuit board. The metal contact pads provide power and data communications for the chip in the package. The printed circuit board may have other features as well, such as a power supply, a heat sink, a fan, and the like.
One particular failure mode of board-level packages is solder joint failure, where the electrical connections to the chip are damaged because the solder fails to make proper contact with the contact pads on the printed circuit board or on the chip. A cause for some solder joint failures is printed circuit board bending due to mechanical shock. The mechanical shock may be caused by shipping or field use of a product that includes the board-level package. Another cause of mechanical shock includes JEDEC testing that subjects the board-level package to a drop test. Such JEDEC testing is described, e.g., in JEDEC Standard No. 22-B111.
The mechanical shock can cause bending of the printed circuit board. If the printed circuit board is considered to lie in the x-y plane, the bending includes deviation from the x-y plane by the edges relative to the center, often in an under-damped, oscillatory motion. The oscillatory bending can cause damage to the electrical contacts where the solder balls touch the contact pads. Current solutions to minimize damage due to bending include use of larger contact pads for the solder balls, use of thinner chip packages, and use of metal supports. However, such conventional solutions may not provide adequate damage prevention in many scenarios. Therefore, there is a need for a better technique to prevent damage from mechanical shock, especially during JEDEC testing.